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HD Serial digital interface (SDI) Signal

Serial digital interface (SDI) is a family of digital video interfaces first standardized by SMPTE (The Society of Motion Picture and Television Engineers) in 1989.[1][2] For example, ITU-R BT.656 and SMPTE 259M define digital video interfacesused for broadcast-grade video. A related standard, known as high-definition serial digital interface (HD-SDI), is standardized in SMPTE 292M; this provides a nominal data rate of 1.485 Gbit/s.[3]

Additional SDI standards have been introduced to support increasing video resolutions (HD, UHD and beyond), frame rates, stereoscopic (3D) video, and color depth. Dual link HD-SDI consists of a pair of SMPTE 292M links, standardized bySMPTE 372M in 1998;[2] this provides a nominal 2.970 Gbit/s interface used in applications (such as digital cinema or HDTV 1080P) that require greater fidelity and resolution than standard HDTV can provide. 3G-SDI (standardized in SMPTE 424M) consists of a single 2.970 Gbit/s serial link that allows replacing dual link HD-SDI. As of August 2014, 6G-SDI and 12G-SDIproducts are already in the market, although their corresponding standards are still in proposal phase.[4]

These standards are used for transmission of uncompressed, unencrypted digital video signals (optionally including embedded audio and time code) within television facilities; they can also be used for packetized data. Coaxial variants of the specification range in length but are typically less than 300 meters. Fiber optic variants of the specification such as 297M allow for long-distance transmission limited only by maximum fiber length and/or repeaters. SDI and HD-SDI are usually only available in professional video equipment because

various licensing agreements restrict the use of unencrypted digital interfaces, such as SDI, prohibiting their use in consumer equipment.

Several professional video and HD-video capable DSLR cameras and all uncompressed video capable consumer cameras use

the HDMI interface, often called Clean HDMI. There are various mod kits for existing DVD players and other devices, which allow a user to add a serial digital interface to these devices.

 

Electrical interface

 

The various serial digital interface standards all use (one or more) coaxial cables with BNC connectors, with a nominal impedance of

75 ohms. This is the same type of cable used in analog video setups, which potentially makes for easier upgrades (though higher quality cables may be necessary for long runs at the higher bitrates). The specified signal amplitude at the source is 800 mV (±10%) peak-to-peak; far lower voltages may be measured at the receiver owing to attenuation. Using equalisation at the receiver, it is possible to send

 

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270 Mbit/s SDI over 300 metres without use of repeaters, but shorter lengths are preferred. The HD bitrates have a shorter maximum run length, typically 100 meters.[5][6]

Uncompressed digital component signals are transmitted. Data is encoded in NRZI format, and a linear feedback shift register is used to scramble the data to reduce the likelihood that long strings of zeroes or ones will be present on the interface. The interface is self- synchronizing and self-clocking. Framing is done by detection of a special synchronization pattern, which appears on the (unscrambled)

serial digital signal to be a sequence of ten ones followed by twenty zeroes (twenty ones followed by forty zeroes in HD); this bit pattern is not legal anywhere else within the data payload.

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Standards

 

Standard

 

Name

 

Introduced

 

Bitrates

 

Example video formats

 

SMPTE 259M

 

SD-SDI

 

1989[2]

 

270 Mbit/s, 360 Mbit/s, 143 Mbit/s, and 177 Mbit/s

 

480i, 576i

 

SMPTE 344M

 

ED-SDI

 

540 Mbit/s

 

480p, 576p

 

SMPTE 292M

 

HD-SDI

 

1998[2]

 

1.485 Gbit/s, and 1.485/1.001 Gbit/s

 

720p, 1080i

 

SMPTE 372M

 

Dual Link HD-SDI

 

2002[2]

 

2.970 Gbit/s, and 2.970/1.001 Gbit/s

 

1080p

 

SMPTE 424M

 

3G-SDI

 

2006[2]

 

2.970 Gbit/s, and 2.970/1.001 Gbit/s

 

1080p

 

 

SMPTE ST-2081*

 

6G UHD-SDI

 

6 Gbit/s

 

4Kp30

 

SMPTE ST-2082*

 

12G UHD-SDI

 

12 Gbit/s

 

4Kp60

 

Non-return-to-zero

From Wikipedia, the free encyclopedia

(Redirected from NRZI)

 

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This article includes a list of references, related reading or external links, but its sources remain unclear because it lacks inline citations. Please improve this article by introducing more precise citations. (January 2013)

 

 

The binary signal is encoded using rectangular pulse amplitude modulation with polar non-return-to-zero code

 

In telecommunication, a non-return-to-zero (NRZ) line code is a binary code in which ones are represented by onesignificant condition, usually a positive voltage, while zeros are represented by some other significant condition, usually a negative voltage, with no other neutral or rest condition. The pulses in NRZ have more energy than a return-to-zero(RZ) code, which also has an additional rest state beside the conditions for ones and zeros. NRZ is not inherently aself-clocking signal, so some additional synchronization technique must be used for avoiding bit slips; examples of such techniques are a run length limited constraint and a parallel synchronization signal.

 

For a given data signaling rate, i.e., bit rate, the NRZ code requires only half the baseband bandwidth required by theManchester code (the passband bandwidth is the same). When used to represent data in an asynchronous communication scheme, the absence of a neutral state requires other mechanisms for bit synchronization when a separate clock signal is not available.

NRZ-Level itself is not a synchronous system but rather an encoding that can be used in either a synchronous or asynchronous transmission environment, that is, with or without an explicit clock signal involved. Because of this, it is not strictly necessary to discuss how the NRZ-Level encoding acts "on a clock edge" or "during a clock cycle" since all transitions happen in the given amount of time representing the actual or implied integral clock cycle. The real question is that of sampling—the high or low state will be received correctly provided the transmission line has stabilized for that bit when the physical line level is sampled at the receiving end.

However, it is helpful to see NRZ transitions as happening on the trailing (falling) clock edge in order to compare NRZ-Level to other encoding methods, such as the mentioned Manchester code, which requires clock edge information (is the XOR of the clock and NRZ, actually) see the difference between NRZ-Mark and NRZ-Inverted.

 

Bit rates

Several bit rates are used in serial digital video Signal:

 

 

Data format

 

In SD and ED applications, the serial data format is defined to 10 bits wide, whereas in HD applications, it is 20 bits wide, divided into two parallel 10-bit datastreams (known as Y and C). The SD datastream is arranged like this:

Cb Y Cr Y' Cb Y Cr Y'

 

whereas the HD datastreams are arranged like this:

 

Y

Y Y' Y Y' Y Y' Y Y'

C

Cb Cr Cb Cr Cb Cr Cb Cr

 

For all serial digital interfaces (excluding the obsolete composite encodings), the native color encoding is 4:2:2 YCbCr format. The luminance channel (Y) is encoded at full bandwidth (13.5 MHz in 270 Mbit/s SD, ~75 MHz in HD), and the two chrominance channels (Cb and Cr) are subsampled horizontally, and encoded at half bandwidth (6.75 MHz or 37.5 MHz). The Y, Cr, and Cb samples are co-sited (acquired at the same instance in time), and the Y' sample is acquired at the time halfway between two adjacent Y samples.

In the above, Y refers to luminance samples, and C to chrominance samples. Cr and Cb further refer to the red and blue "color difference" channels; seeComponent Video for more information. This section only discusses the native color encoding of SDI;

 

other color encodings are possible by treating the interface as a generic 10-bit data channel. The use of other colorimetry encodings, and the conversion to and from RGB colorspace, is discussed below.

Video payload (as well as ancillary data payload) may use any 10-bit word in the range 4 to 1,019 (00416 to 3FB16) inclusive; the values 0–3 and 1,020–1,023 (3FC163FF16) are reserved and may not appear anywhere in the payload. These reserved words have two purposes; they are used both for Synchronization packets and for Ancillary data headers.

Synchronization packets

 

A synchronization packet (commonly known as the timing reference signal or TRS) occurs immediately before the first active sample on every line, and immediately after the last active sample (and before the start of the horizontal blanking region). The synchronization packet consists of four 10-bit words, the first three words are always the same—0x3FF, 0, 0; the fourth consists of 3 flag bits, along with an error correcting code. As a result, there are 8 different synchronization packets possible.

In the HD-SDI and dual link interfaces, synchronization packets must occur simultaneously in both the Y and C datastreams. (Some delay between the two cables in a dual link interface is permissible; equipment which supports dual link is expected to buffer the leading link in order to allow the other link to catch up). In SD-SDI and enhanced definition interfaces, there is only one datastream, and thus only one synchronization packet at a time. Other than the issue of how many packets appear, their format is the same in all versions of the serial-digital interface.

The flags bits found in the fourth word (commonly known as the XYZ word) are known as H, F, and V. The H bit indicates the start of horizontal blank; and synchronization bits immediately preceding the horizontal blanking region must have H set to one. Such packets are commonly referred to as End of Active Video, or EAV packets. Likewise, the packet appearing immediately before the start of the active video has H set to 0; this is the Start of Active Video or SAV packet.

Likewise, the V bit is used to indicate the start of the vertical blanking region; an EAV packet with V=1 indicates the following line (lines are deemed to start at EAV) is part of the vertical interval, an EAV packet with V=0 indicates the following line is part of the active picture.

The F bit is used in interlaced and segmented-frame formats to indicate whether the line comes from the first or second field (or segment). In progressive scanformats, the F bit is always set to zero.

Line counter and CRC

 

In the high definition serial digital interface (and in dual-link HD), additional check words are provided to increase the robustness of the interface. In these formats, the four samples immediately following the EAV packets (but not the SAV packets) contain a cyclic redundancy check field, and a line count indicator. The CRC field provides a CRC of the preceding line (CRCs are computed independently for the Y and C streams), and can be used to detect bit errors in the interface. The line count field indicates the line number of the current line.

The CRC and line counts are not provided in the SD and ED interfaces. Instead, a special ancillary data packet known as an EDH packet may be optionally used to provide a CRC check on the data.

Line and sample numbering

 

Each sample within a given datastream is assigned a unique line and sample number. In all formats, the first sample immediately following the SAV packet is assigned sample number 0; the next sample is sample 1; all the way up to the XYZ word in the following SAV packet. In SD interfaces, where there is only one datastream, the 0th sample is a Cb sample; the 1st sample a Y sample, the 2nd sample a Cr sample, and the third sample is the Y' sample; the pattern repeats from there. In HD interfaces, each datastream has its own sample numbering—so the 0th sample of the Y datastream is the Y sample, the next sample the Y' sample, etc. Likewise, the first sample in the C datastream is Cb, followed by Cr, followed by Cb again.

Lines are numbered sequentially, starting from 1, up to the number of lines per frame of the indicated format (typically 525, 625, 750, or 1125 (Sony HDVS)). Determination of line 1 is somewhat arbitrary; however it is unambiguously specified by the relevant standards. In 525-line systems, the first line of vertical blank is line 1, whereas in other interlaced systems (625 and 1125-line), the first line after the F bit transitions to zero is line 1.

Note that lines are deemed to start at EAV, whereas sample zero is the sample following SAV. This produces the somewhat confusing result that the first sample in a given line of 1080i video is sample number 1920 (the first EAV sample in that format), and the line ends at the following sample 1919 (the last active sample in that format). Note that this behavior differs somewhat from analog video interfaces, where the line transition is deemed to occur at the sync pulse, which occurs roughly halfway through the horizontal blanking region.

Author: Thomas Stewart




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